This invention generally relates to cache memory, and in particular, to embedded dynamic access memory (EDRAM) macro disablement in cache memory.
Conventionally, redundancies in EDRAM macros and EDRAM macro sparing may be employed to circumvent a limited number of defects within a cache memory. The redundancies may be formed as spare portions within the cache memory which may be accessed through arranged circuitry. Thus, if portions of a cache memory are defective, particularly within an EDRAM macro, a portion of the redundancies may be utilized to replace the defective portions. However, if the available spare portions for the cache memory are all utilized and subsequent defects exist, the cache memory cannot be used and must be discarded.
In relatively large cache memories, EDRAM macro sparing and redundancies are not practical. For example, a large cache memory may include a plurality of data paths and multiple address sliced cache banks. In order to include an acceptable number of redundancies for EDRAM macros, the arranged circuitry for redundancy activation would require much more space than may be available on large cache memory chips, in addition to causing increased difficulties in design, fabrication, and control resulting from the heavily populated circuitry associated with the redundancies.